CEG/EE 260-01 Digital Computer Hardware/Switching Circuits

Fall 2005, 6:05-7:20 Tue., Thr., at 153 RC

Instructor: Jack Jean

Office Hours: 1:40-2:40 PM, M, W & 5-6 PM, T, Thr, 334 RC, 775-5106, jjean@cs.wright.edu

Textbook: Mano and Kime, Logic and Computer Design Fundamentals, 3rd Edition, Prentice-Hall, 2004

Weekly Schedule:

Week	Contents	Read	Preparation
1	Intro to digital design, number systems, gates	1.1-1.6, 2.1	Lab 1
2	Boolean algebra and combinational circuit design	2.2-2.3
3	Boolean algebra, Karnaugh maps	2.4	Lab 2
4	TEST #1; Karnaugh maps	2.5	Lab 3
5	Karnaugh maps, circuit design and analysis	2.6-2.9, 3.1-3.6	Lab 4
6	Decoders, encoders, and multiplexers	4.1-4.6
7	Latches and flip-flops; TEST #2	6.1-6.3	Lab 5
8	Flip-flips, Registers	6.6, 7.1	Lab 6
9	IC Counters	7.6	Lab 7
10	Binary arithmetic, adders, and subtractors	5.1-5.4

Grading: Final letter grade: 90+ (A), 80+ (B), 70+ (C), 60+ (D), otherwise (F).

• Lab. - 30%. You must attain at least 60% in Laboratory to pass this course.
• HW - 10%
• Quiz - 10%. Quizzes, given at the beginning of classes, will be unannounced, closed book, no calculator allowed.
• Test 1 - 15%; September 27, Tuesday, closed book.  You may bring in one sheet of note and a calculator.
• Test 2 - 15%;  October 20, Thursday, not comprehensive, closed book.  You may bring in one sheet of note and a calculator.
• Final - 20%; November 17, Thursday, 8-10PM, not comprehensive, closed book.  You may bring in one sheet of note and a calculator.