Digital signal processing algorithms with multiple shift-invariant dependence graphs (DGs) can be mapped to FPGA hardware in many different types of systolic processor arrays. Because of the finite amount of hardware resources, the problem is to use a ``right'' amount of hardware in a specific configuration so to maximize the processing speed.

In this dissertation, the problem of finding the right processor array configuration is formulated as a constrained optimization problem where the cost function includes not only the cost of individual processor arrays but also the cost of interfacing circuits. Five heuristic algorithms are presented for the optimization problem. Among them, both the L-th axial neighbor algorithm and the simulated annealing algorithm produce good results on a test case.

Simulation results on the test case also indicate that the initial configuration is important in getting a good configuration for both algorithms. The L-th axial neighbor algorithm has the extra advantage of requiring less amount of performance tuning.