JOURNAL PUBLICATIONS

1. J. M. Emmert, M. Abramovici, and C. E. Stroud, “On-line, Fault Tolerance for FPGA Logic Blocks,” submitted to the IEEE Transactions on VLSI Systems, Accepted for publication, 2007.

2. J. A. Cheatham, J. M. Emmert, and S. R. Baumgart, “A Survey of Fault Tolerant Methodologies for FPGAs,” ACM Transactions on Design Automation of Computer Systems, Volume 11, Number 2, pp. 501-533, April, 2006.

3. M. Abramovici, C. E. Stroud, J. M. Emmert, “On-line BIST and BIST Based Diagnosis of FPGA Logic Blocks,” IEEE Transactions on VLSI Systems, Volume 12, Number 12, pp. 1284-1294, December 2004.

4. J. M. Emmert, S. Lodha, and D. K. Bhatia, “On Using Tabu Search for Design Automation for VLSI Systems,” Journal of Heuristics, Volume 9, Number 1, pp. 75-90, January 2003.

5. J. M. Emmert and D. K. Bhatia, “Two-Dimensional Placement Using TABU Search,” Journal of VLSI Design, Volume 12, Number 1, pp. 13-23, December 2001.

6. C. E. Stroud, J. R. Bailey, and J. M. Emmert, “A New Method for Testing Re-programmable Programmable Logic Arrays,” in Journal of Electronic Testing Theory and Applications, Volume 16. Number 6, pp. 635-640, December 2000.

7. J. M. Emmert and D. K. Bhatia, “A Fault Tolerant Technique for FPGAs,” in Journal of Electronic Testing Theory and Applications, Volume 16. Number 6, pp. 591-606, December 2000.

8. J. M. Emmert, C. E. Stroud, J. Cheatham, A. Taylor, P. Kataria, and M. Abramovici, “Performance Penalty for Fault Tolerance in Roving Self Testing Areas (STARs),” Lecture Notes in Computer Science, Springer-Verlag , Volume 1896, pp. 545-554, August, 2000.

9. J. M. Emmert and D. K. Bhatia, “Tabu Search: Ultra Fast Placement for FPGAs,” Lecture Notes in Computer Science, Springer-Verlag, Volume 1673, pp. 81-90, September, 1999.

10. J. M. Emmert, A. Randhar, and D. K. Bhatia, “Fast Floorplanning for FPGAs,” Lecture Notes in Computer Science, Springer-Verlag, Volume 1482, pp. 129-138, September, 1998.

11. J. M. Emmert and D. K. Bhatia, “Reconfiguring FPGA Mapped Designs with Applications to Fault Tolerance and Reconfigurable Computing,” Lecture Notes in Computer Science, Springer-Verlag, Volume 1304, pp. 141-150, August, 1997.

CONFERENCE PUBLICATIONS

1. J. Buck, J. Tsui, S. Hary, D. Schwab, and J. M. Emmert, “Monobit Receiver Architecture and Signal Threshold Determination,” GOMACTech-07, To Appear, March, 2007.

2. P. Buxz, G. Creech, and J. M. Emmert, “Parameterizable Digital Receiver with Decimation Filter for High Update Rate,” GOMACTech-07, To Appear, March, 2007.

3. J. Emmert, J. Cheatham, and H. Axtell, “Analysis and Test of a Spectral, Mixed Signal BIST Technique for Systems on a Chip Applications,” IEEE North Atlantic Test Workshop, May, 2006.

4. S. Singh, A. Roy, K. Rattan, and J. M. Emmert, “Performance Tradeoffs of Hardware/Software Implementation of a Fuzzy Logic Controller on Programmable Hardware,” 2005 IEEE North American Fuzzy Information Processing Society Soft Computing for Real World Applications Conference, June, 2005.

5. J. M. Emmert and J. A. Cheatham, “Integrated Spectral BIST Technique for IRFFE Systems,” GOMACTech-05, To Appear, April, 2005.

6. J. M. Emmert and J. A. Cheatham, “A Monolithic Spectral BIST Technique for Control or Test of Analog or Mixed-Signal Circuits,” 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November, 2003.

7. J. M. Emmert, J. A. Cheatham and B. Jagannathan, “An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals,” 2003 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, November, 2003.

8. M. Abramovici, C. E. Stroud, and J. M. Emmert, “Using Embedded FPGAs for SoC Yield Enhancement,” Proceedings of the 2002 ACM/IEEE Design Automation Conference, 2002.

9. J. M. Emmert, C. E. Stroud, S. R. Baumgart, P. Kataria, and M. Abramovici, “On-line Fault Tolerance for FPGA Interconnect with Roving STARs,” Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October, 2001.

10. J. M. Emmert and J. A. Cheatham, “On-line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router,” Proceedings of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October, 2001.

11. M. Abramovici, J. M. Emmert, and C. E. Stroud, “Roving STARs: An Integrated Approach to On-Line Testing, Diagnosis, and Fault Tolerance for FPGAs in Adaptive Computing Systems,” Proceedings of the IEEE Evolvable Hardware Conference, pp. 75-94, July, 2001.

12. C. E. Stroud, M. Lashinsky, J. Nall, J. Emmert, and M. Abramovici, “On-line BIST and Diagnosis of FPGA Interconnect Using Roving STARs,” Proceedings of the IEEE International Online Test Workshop, 2001.

13. C. E. Stroud, J. M. Emmert, A. Taylor, and J. T. Ferry, “Recovering Faulty Processing Elements in VLSI Processor Arrays,” Autotestcon, September, 2001. (received Best Paper Award)

14. P. Kataria and J. M. Emmert, “Window Rip-up for Faster Testing and Fault Tolerance in FPGAs,” Autotestcon, September, 2001.

15. T. Slaughter, C. Stroud, J. Emmert, and B. Skaggs, “Fault Injection Emulator for Field Programmable Gate Arrays,” Proceedings of the International Society of Optical Engineering ITCOM, pp. 1-9, 2001.

16. J. R. Heath, N. J. Vocke, C. E. Stroud, and J. M. Emmert, “Routing Algorithms for Programmable Logic Device Design and Manufacturing Test Development,” Autotestcon, September, 2001.

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