The contributions of our work are in performance improvement of parallel logic simulation.The major contributions of this dissertation are presented to be the following:

1. An improved concurrency preserving partitioning (iCPP) algorithm was developed which    significantly improves  the simulation performance for low-granularity applications  with a large number of nodes. This is the first significant research considering concurrency topic in partitioning algorithm. Our experimental results for the iCPP algorithm show significant improvement in the performance of parallel logic simulation over other partitioning algorithms. To the best of our knowledge, the obtained speedups may be the best known results in parallel logic simulation. This iCPP algorithm can be applied to the problems of task graph assignment and load balancing on distributed-memory parallel machines.
2. A concurrency metric was proposed to measure the quality of partitioning algorithms in terms of the degree of concurrency of a partitioned directed graph before the execution of real parallel simulations. With this metric, it was shown that concurrency was an important factor in predicting parallel simulation performance which has been overlooked previously.
3. An event-lookahead technique was proposed to reduce the multiple evaluation overhead and stabilize the simulation.  As a result, it is proposed to provide consistently good performance of parallel logic simulation for different circuits. It can be considered as a good parallelization of cycle-based simulation or compiled-code simulation, which has good performance in sequential simulation. The protocol is more scalable in terms of the number of events generated when compared to other parallel discrete event simulation protocols. Therefore, it is better for extremely large circuits when a large number of processors are used. It also works very well and consistently for zero-delay, unit-delay, and multiple-delay model of different circuits.